1. Field of the Invention
The present invention relates to a multilayer printed circuit board, and a manufacturing method thereof.
2. Description of the Related Art
It has been common that, a printed circuit board has a multilayer (blind via hole (BVH)) structure including build-up layers to be mounted with electronic components such as semiconductor components etc. The multilayer printed circuit board includes multiple product portions linked with a portion that is to be removed in manufacturing process by joints. A plurality of semiconductor components can be intensively mounted on the product portions, which enhances mounting efficiency of the electronic components.
An outline structure of a conventional multilayer printed circuit board 10 is explained with reference to FIGS. 8 and 9. FIG. 8 is a plan view of the multilayer printed circuit board 10, and FIG. 9 is a cross section of the multilayer printed circuit board 10.
The printed circuit board 10 includes product portions 11 with electronic components etc. mounted thereon, a backing plate 12 that is to be removed in manufacturing process, joints 13 on perforations, and slits 14. The product portions 11 are linked to the backing plate 12 by the joints 13.
Further, the printed circuit board 10 includes an insulating material 10a, conductive patterns 15 on the front and back surfaces of the insulating material 10a, and internal conductive patterns 16 inside the printed circuit board 10. The conductive patterns 15 and the internal conductive patterns 16 are linked by a plurality of vias 17. Thus, the printed circuit board 10 has a multilayer structure in which a plurality of patterns are electrically connected to each other. Solder mask 18 is applied to the upper and lower surfaces of the product portion 11.
The solder mask 18 prevents electrical coupling of electrical circuit patterns of the adjacent conductive patterns 15. As shown in FIG. 9, in the printed circuit board 10, a solder ball of the electronic components is coupled with a solder ball on the conductive pattern 15 such that the electronic components are mounted on the printed circuit board 10. After the electronic components are heat-bonded to the printed circuit board 10 by reflow soldering, the joints 13 (shown in FIG. 8) are cut to separate the product portions 11, and the printed circuit board 10 is embedded in an electronic device.
Sometimes warpage occurs in the printed circuit board 10 after the reflow process due to the heat of the reflow process. Some conventional technologies have been proposed to overcome this warpage problem of the printed circuit board.
Japanese Patent Laid-Open Publication No. 2003-258158 discloses a manufacturing method of a semiconductor device. In the conventional method, multiple bracket holes or grooves are formed in longitudinal and lateral directions along a peripheral area of a printed circuit board to suppress warping of a multi-wire board such as a Large Scale Integrated Package (LSI-PKG).
Japanese Patent Laid-Open Publication No. H8-274418 discloses a structure of the printed circuit board, in which a tapered hole is formed on a splitting line of a board, the tapered hole is filled with reinforcing material of resin, and, after mounting of components, the reinforcing material is removed by heat. In the disclosed printed circuit board, splitting can be easily carried out at the splitting line of the board, which suppresses warping during mounting of the components.
Japanese Patent Laid-Open Publication No. 2002-290031 discloses a circuit board and a manufacturing method thereof, in which warping is suppressed by applying solder masks in different thicknesses to the front and back surfaces of a printed circuit board, and coupling two boards via a spacer for reinforcement.
Japanese Patent Laid-Open Publication No. H9-172104 discloses a board for a semiconductor device, in which areas to be coated with solder masks are set on the front and back surfaces of the board at a predetermined ratio, and also the solder masks are applied in thicknesses at a predetermined ratio to suppress warping of the board.
Japanese Patent Laid-Open Publication No. 2003-152289 discloses a printed circuit board and a multilayer printed circuit board, in which a board is reinforced by embedding a metal plate in a backing plate of the board to prevent occurrence of warping during the reflow process.
Japanese Patent Laid-Open Publication No. 2001-185576 discloses a semiconductor device, in which dummy wiring is formed on a board to prevent warping of the board.
Japanese Patent Laid-Open Publication No. 2002-324952 discloses a printed circuit board, in which the entire surface of a backing plate of the printed circuit board is covered with copper foils, and the copper foils are coupled by vias to enhance the rigidity of the backing plate and suppress warping of the board.
However, in the conventional technologies, warping and deformation of a printed circuit board still occurs due to heat of curing (thermosetting) in the reflow process. To be specific, as shown in FIG. 10, because the same material is used for solder masks that are respectively applied to both the surfaces of the printed circuit board, warping directions of the solder masks during the reflow process are nearly the same. Accordingly, the printed circuit board (the product portions 11) is also bent with warping of the solder mask.
If the printed circuit board warps, it is difficult to solder the electronic components to the product portions, and the electronic components are not securely bonded to the product portions. This results in reduction in yield, quality, and reliability in manufacturing the printed circuit board is reduced.